Renesas - DDR5 data buffer for high-performance server and cloud service applications | 黑森爾電子
聯繫我們
SalesDept@heisener.com +86-755-83210559 ext. 815
Language Translation

* Please refer to the English Version as our Official Version.

Renesas - DDR5 data buffer for high-performance server and cloud service applications

Technology Cover
發佈日期: 2020-12-09, Renesas Electronics America

Renesas Electronics Corporation provides a new type of high-speed, low-power DDR5 data buffer for data center, server and high-performance workstation applications.

In the past few years, the development of real-time analytics, machine learning, AI, HPC and other memory and bandwidth demanding applications has provided explosive growth in server memory bandwidth requirements. The company's new JEDEC-compliant DDR5 data buffer 5DB0148 greatly improves the speed and latency of LRDIMMs, which have developed into the basic storage technology for such new applications. The first-generation DDR5 LRDIMM based on the company's components has increased bandwidth by more than 35% compared to DDR4 LRDIMM running at 3200MT/s.

Rami Sethi, vice president of Renesas Electronics’ Data Center Business Unit, said: “As a complete DDR5 solution provider in the industry, we are working closely with customers and ecosystem partners to put a broad portfolio of memory solutions into production.” Our DDR5 data buffers are essential for the realization of high-performance DRAM solutions (such as LRDIMMs, spare high-density modules and heterogeneous memory solutions), all of which support a new generation of high-performance computing applications."

The DDR5 data buffer provides the largest channel openness for systems with heavier loads through the combination of data alignment, capacitive load reduction and signal recovery technology. This allows server motherboards with a large number of memory channels and slots and complex routing topologies to run at maximum speed even with high-density memory. In addition, improvements in the DDR5 module definition provide a lower power supply voltage (1.1V in DDR4 versus 1.2V in DDR4), voltage regulation on DIMMs, and implementation of advanced control plane architecture by using SPD hubs and modern control bus communication . As I3C.

相關產品