Texas Instruments has introduced a new family of clock generators with ultra-low jitter of 100 femtoseconds (fs) and flexible "unique" pin control options.
Compared with traditional reference clock solutions, the jitter performance of the new clock generator enables system designers to optimize the system timing margin and bit error rate (BER) to reduce data transmission errors. This allows for more reliable communications, networks, servers, computing and high-performance industrial equipment. The company said that the LMK033x8 clock generator also has multiple features that can shorten the design cycle by simplifying prototyping and evaluation.
Key Features: 1-Ultra-low jitter performance enables flexible jitter budgets: up to two high-performance PLLatinum N frequency-divided phase-locked loops (PLLs) with 8 outputs for ultra-low 100 fs rms Jitter performance is on multiple integrated bandwidths (1KHz-5MHz and 12KHz-20MHz). Designers can use ultra-low jitter to improve their system BER and increase the reliability of their telecommunications infrastructure equipment. 2 – Flexible, simple configuration: Compared to one-time programmable memories provided by competitors, unique pin-mode control features allow designers to easily select from 71 pre-programmed frequency start-up plans. Integrated electrical erasable programmable read-only memory (EEPROM) makes customization easy, and the I2C interface gives system designers complete control over device configuration. 3-Reduce Design Cycle Time: Glitch-free fine / rough frequency margins allow designers to simplify system stress and compliance testing during prototype design verification and process verification (DVT / PVT). 4 – Not affected by power supply noise: The integrated low-dropout regulator (LDO) can resist power supply noise without requiring complex filter designs.
An evaluation module (EVM) allows designers to quickly and easily evaluate equipment. The LMK03328EVM is available now, and the LMK03318EVM will be available in the fourth quarter of 2015.
TI's WEBENCH Clock Architect tool simplifies the design process for the LMK033x8 series and other TI clock and timing devices. The tool can recommend single-device or multi-device clock tree solutions from an extensive device database to meet system requirements. The company says it has PLL filter design, phase noise simulation, and the ability to enable designers to optimize clock tree designs for their performance and cost requirements.
